 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 1 of 37 general description the ds28e04 -100 is a 4096 - bit, 1 - wire ? eeprom chip with seven address inputs. the address inputs are directly mapped into the 1 - wire 64 - bit device id number to easily enable the host system to identify the physical loca tion or functional association of the ds28e04 -100 in a multidevice 1 - wire network en - vironment. the 4096-bit eeprom array is configured as 16 pages of 32 bytes with a 32 byte scratchpad to perform write operations. eeprom memory pages can be individually w rite protected or put in eprom - emulation mode, where bits can only be changed from a 1 to a 0 state. in addition to the memory, the ds28e04 -100 has two general - purpose i/o ports that can be used for input or to generate level and/or pulse out puts. activit y registers also capture port activity for state change monitoring. the ds28e04 - 100 commu nicates over the single - contact 1- wire bus. the communication follows the standard maxim 1 - wire protocol. applications autoconfiguration of mod ular systems such as central - office switches, cellular base stations, access products, optical network units, and pbxs accessory/pcb identification typical operating ci rcuit px.y c r pup v cc io v cc pol p1 p0 gnd a0 a6 ds28e04 #1 io v cc pol p1 p0 gnd a0 a6 ds28e04 #7 rst1 rst0 led features ? 4096 bits of eeprom memory partitioned into 16 pages of 256 bits ? seven address inputs for physical location configuration ? two general - purpose pio pins with pulse- generation capability ? individual memory pages can be permanently write - protected or put in otp eprom - emulation mode (write to 0) ? commun icates to host with a single digital signal at 15.3kbps or 111kbps using 1 - wire protocol ? parasitic or v cc powered ? conditional search based on pio status or pio activity ? switchpoint hysteresis and filtering to optimize performance in the presence of noise ? reads and writes over a wide 2.8v to 5.25v voltage range from - 40c to +85c ? 16- pin, 150- mil so package ordering information part temp range pin - package ds28e04s - 100 + - 40c to +85c 16 so ds28e04s - 100 + t - 40c to +85c 16 so (2.5k pieces) + indicates lead(pb) - free/rohs - compliant package. t = tape and reel. pin configuration so (150 mils) commands, registers, and modes are capitalized for clarity. 1 - wire is a r egistered trademark of maxim integrated products, inc. ds28e04 - 100 4096- bit addressable 1- wire eeprom with pio 19 - 6134 ; rev 1 2 /11
ds28e04 - 100: 4096- bit 1 - wire addressable eeprom with pio 2 of 37 absolute maximum rat ings all pins: voltage to gnd - 0.5v, +6v all pins: sink current 20ma operating t emperature range - 40c to +85c junction temperature +150c storage temperature range - 55 c to + 12 5 c lead t emperature (soldering , 10s) +300c soldering temperature (reflow) +260c stresses beyond those listed under abs olute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to the absolute maximum rating conditions for extended periods may affect device reliability. electrical characteristics (v pup = 2.8v to 5.25v, v cc = v pup , not connected or grounded, t a = - 40c to +85c.) parameter symbol conditions min typ max units ground current i gnd (notes 1, 2, 3) 20 ma supply current i cc v cc = v pup (note 3) 1 ma standby supply current i ccs device idle; a0 to a6 not connected 11 a pins a0 to a6 input low voltage v ila (note 1) 0.30 v input high voltage v iha v x = max(v pup , v cc ) (note 1) v x - 0.3v v input load current i la pin at gnd (note 4) - 1.1 a pol pin input low voltage v ilpol (note 1) 0.30 v input high voltage v ihpol v x = max(v pup , v cc ) (note 1) v x - 0.3v v leakage current i lkpol pin at 5.25v 1 a pio pins input low voltage v ilp (note 1) 0.30 v input high voltage v ihp v x = max(v pup , v cc ) (note 1) v x - 0.3v v output low voltage at 4ma v olp (note 5) 0.4 v leakage current i lkp pin at 5.25v 1 a minimum sensed p io pulse t pwmin (note 6) 1 10 s output pulse duration t pulse (note 7) 250 1000 ms io pin general data 1 - wire pullup resistance r pup (notes 1, 8) 0.3 2.2 k ? input capacitance c io (notes 3, 9) 100 800 pf input load current i l io pin at v pup , a0 to a6 not connected , v cc at gnd 0.05 11.00 a io pin at v pup , a0 to a6 not connected , v cc at v pup 0.05 8.25 high - to - low switching threshold v tl (notes 3, 10, 11) 0.46 4.40 v input low voltage v il (notes 1, 12) 0.3 v input hi gh voltage v ih v x = max(v pup , v cc ) (note 1) v x - 0.3v v low - to - high switching threshold v th (notes 3, 10, 13) 1.0 4.9 v switching hysteresis v hy (notes 3, 10, 14) 0.21 1.70 v output low voltage v ol at 4ma current load (note 5) 0.4 v recovery tim e (notes 1, 15) t rec standard speed, r pup = 2.2k ? 5 s overdrive speed, r pup = 2.2k ? 2 overdrive speed, directly prior to reset pulse; r pup = 2.2k ? 5 rising - edge hold - off time (note 3) t reh standard speed (note 16) 0.5 5.0 s overdrive speed not applicable (0) ds28e04 - 100: 4096- bit 1 - wire addressable eeprom with pio 3 of 37 parameter symbol conditions min typ max units time slot duration (note 1) t slot standard speed 65 s overdrive speed 9 io pin, 1 - wire reset, presence dete ct cycle reset low time (note 1) t rstl standard speed, v pup > 4.5v 480 640 s standard speed (note 17) 504 640 overdrive speed, v pup > 4.5v 48 80 overdrive speed (note 17) 53 80 presence - detect high time t pdh standard speed 15 60 s overdrive speed (note 17) 2 7 presence - detect fall time (notes 3, 18) t fpd standard speed, v pup > 4.5v 1.10 3.75 s standard speed 1.1 7.0 overdrive speed 0 1.1 presence - detect low time t pdl standard speed 60 240 s overdrive speed, v pup > 4.5v 8 24 overdrive speed (note 17) 8 26 presence - detect sample time (note 1) t msp standard speed, v pup > 4.5v 64 75 s standard speed 67 75 overdrive speed 8.1 10 io pin, 1 - wire write write - 0 low time (note s 1 , 19 ) t w0l standard speed 60 120 s overdrive speed (note 17) 7 16 write - 1 low time (notes 1, 19) t w1l standard speed 5 15 s overdrive speed 1 2 io pin, 1 - wire read read low time (notes 1, 20) t rl standard speed 5 15 - s overdrive speed 1 2 - read sample time (notes 1, 20) t msr standard speed t rl + 15 s overdrive speed t rl + 2 eeprom programming current i prog (note 21) 1 ma programming time t prog (note 22) 10 ms write/erase cycles (endurance) (note 23) n cy at +25c 200k ? at +85c (worst case) 50k data retention (notes 23, 24) t dr at +85c (worst case) 40 years note 1: system requirement. note 2: maximum instantaneous pulldown current through all pins combined. note 3: guaranteed by design, simulation only. not production tested. note 4: this load current is caused by the internal weak pullup, which asserts a logical 1 to address pins that are not connected. the logical state of the address pins must not change during the execution of rom function commands during those time slots in which these bits are relevant. note 5: the i - v characteristic is linear for voltages less than 1v. note 6: width of the narrowest pulse that trips the activity latch. back to back pulses that are active for < t pwmin (max) and that have an intermediate inactive time < t pwmin (max) are not guaranteed to be filtered. note 7: the pulse function requires that v cc power is available; otherwise the command will not be executed. note 8: maximum allowable pullup resistance is a function of the number of 1 - wire devices in the system and 1 - wire recovery times. the specified value here applies to systems with only one device and with the minimum 1 - wire recovery times. for more heavily loaded systems, an active pullup such as that found in the ds2482 - x00, ds2480b, or ds2490 may be required. note 9: capacitance on the data pin could be 8 00pf when v pup is first applied. if a 2.2k ? resistor is used to pull up the data line, 2.5s after v p up has been applied the parasite capacitance will not affect normal communications. note 10: v tl , v th , and v hy are a function of the internal supply volt age , which in parasite power mode, is a function of v p up and the 1 - w ire recovery times. the v th and v tl maximum specifications are valid at v cc = v pup = 5.25v. in any case, v tl < v th < v p up . note 11: voltage below which, during a falling edge on io, a logic 0 is detected. note 12: the voltage on io needs to be less than or equal to v ilmax whenever the master drives the line low. note 13: voltage above which, during a rising edge on io, a logic 1 is detected. note 14: after v th is crossed during a r ising edge on io, the voltage on io has to drop by at least v hy to be detected as logic '0'. note 15: applies to a single ds28e04 - 100 without v cc supply, attached to a 1 - wire line. note 16: the earliest recognition of a negative edge is possible at t reh after v th has been previously reached. note 17: highlighted numbers are not in compliance with legacy 1 - wire product standards. see comparison table. note 18: interval during the negative edge on io at the beginning of a presence detect pulse between th e time at which the voltage is 80% of v p up and the time at which the voltage is 20% of v p up . ds28e04 - 100: 4096- bit 1 - wire addressable eeprom with pio 4 of 37 note 19: in figure 16 represents the time required for the pullup circuitry to pull the voltage on io up from v il to v th . the actual maximum duration for the master to pull the line low is t w1lmax + t f - and t w0lmax + t f - respectively. note 20: in figure 16 represents the time required for the pullup circuitry to pull the voltage on io up from v il to the input high threshold of the bus master. the actu al maximum duration for the master to pull the line low is t rlmax + t f . note 21: current drawn during the eeprom programming interval. if the device does not get v cc power, the pullup circuit on io during the programming interval should be such that the v oltage at io is greater than or equal to v p up (min). if v pup in the system is close to vpup(min) then a low - impedance bypass of r p up that can be activated during programming may need to be added. note 22: the t prog interval begins t rehmax after the traili ng rising edge on io for the last time slot of the e/s byte for a valid copy scratchpad sequence. interval ends once the device's self - timed eeprom programming cycle is complete and the current drawn by the device has returned from i prog to i l or i ccs , res pectively. note 23: not production tested. guaranteed by design or characterization. note 24: eeprom writes can become nonfunctional after the data - retention time is exceeded. long - time storage at elevated temperatures is not recommended; the device can lose its write capability after 10 years at +125c or 40 years at +85c. legacy values ds28e04 - 100 values parameter standard speed overdrive speed standard speed overdrive speed min max min max min max min max t slot (incl. t rec ) 61s (undef) 7s (un def) 65s 1) (undef) 9s (undef) t rstl 480s (undef) 48s 80s 504s 640s 53s 80s t pdh 15s 60s 2s 6s 15s 60s 2s 7s t pdl 60s 240s 8s 24s 60s 240s 8s 26s t w0l 60s 120s 6s 16s 60s 120s 7s 16s 1) intentional change, longer recove ry time requirement due to modified 1 - wire front end. pin description pin name function 1 a3 address bit input (place value = 8), with weak pullup. 2 a2 address bit input (place value = 4), with weak pullup. 3 a1 address bit input (place value = 2), w ith weak pullup. 4 a0 least significant address bit input (place value = 1), with weak pullup. 5, 12 gnd ground reference 6, 11 n.c. not connected 7 v cc optional power supply for the chip; leave unconnected or ground if v cc power is not available . 8 pol power - up polarity (logical state) for p0 and p1; pin has a weak pulldown. 9 p0 remote - controlled i/o pin, open drain with weak pulldown. 10 p1 remote - controlled i/o pin, open drain with weak pulldown. 13 a6 address bit input (place value = 64), with weak pullup. 14 a5 address bit input (place value = 32), with weak pullup. 15 a4 address bit input (place value = 16), with weak pullup. 16 io 1 - wire bus interface. open drain, requires external pullup resistor. detailed description the ds28e 04- 100 combines 4096 bits of eeprom, a 16- byte control page, two general - purpose pio pins, seven external address pins, and a fully featured 1 - wire interface in a single chip. pio outputs are configured as open - drain and provide an on - resis tance of 100 ? m ax. a robust pio channel - access communication protocol ensures that pio output - setting changes occur error - free. the ds28e04 - 100 has an additional memory area called the scratchpad that acts as a buffer when writing to the main memory or the control page. data is first written to the scratchpad from which it can be read back. the copy scratchpad command transfers the data to its final memory location. each ds28e04 - 100 has a device id number that is 64 bits long. the user can define seven bits of this number through address pins. the remaining 57 bits are factory - lasered into the chip. the device id number guarantees unique identification and is used to address the device in a multidrop 1 - wire network environment, where multiple devices reside on a common 1 - w ire bus and operate independently of each other. the ds28e04 - 100 also supports 1 - wire conditional search capability based on pio conditions or power -on- reset activity. the ds28e04 - 100 has an optional v cc supply connection. when an external supply is absent , device power is supplied parasiti cally from the 1 - wire bus. when an external supply is present, pio states are maintained in the absence of the 1 - wire bus power source. applications of the ds28e04 - 100 include autoconfiguration and state monitoring of mo dular systems such as central - office switches, cellular base stations, access products, optical network units, and pbxs, and acces sory/pc board identification. ds28e04 - 100: 4096- bit 1 - wire addressable eeprom with pio 5 of 37 overview the block diagram in figure 1 shows the relationships between the major control and m emory sections of the ds28e04 - 100. the ds28e04- 100 has five main data components: 1) 64- bit device id number, 2) 32- byte scratchpad, 3) sixteen 32 - byte pages of eeprom, 4) special function register, and 5) pio control registers. the hierarchical structure of the 1 - wire protocol is shown in figure 2. the bus master must first provide one of the eight rom function commands, 1) read rom, 2) match rom, 3) search rom, 4) conditional search rom, 5) skip rom, 6) resume, 7) overdrive - skip rom or 8) overdrive- match rom. upon completion of an overdrive rom command byte executed at standard speed, the device enters overdrive mode where all subsequent communication occurs at a higher speed. the protocol required for these rom function commands is described in figure 14. after a rom function command is successfully executed, the memory/control functions become accessible and the master may provide any one of the nine memory/control function commands. the protocol for these commands is described in figure 9. all data is re ad and written least significant bit first. figure 1. block diagram 1 - wire network device id number register 1 - wire function control memory function control unit special function registers 32 - byte scratchpad data memory 16 pages of 32 bytes each crc16 generator a0 a6 io internal v dd pio control registers p0 v cc p1 pol internal v dd ds28e04 - 100: 4096- bit 1 - wire addressable eeprom with pio 6 of 37 figure 2. hierarchical structure for 1 - wire protocol ds28e04 - 100 available commands: command level: data field affected: 1 - wire rom function commands (see figure 14) ds28e04 - specific memory/control function commands (see figure 9) read rom match rom search rom conditio nal search rom skip rom resume overdrive skip overdrive match device id, rc - flag device id, rc - flag device id, rc - flag device id , rc - flag, pio status, cond. search setti ngs rc - flag rc - flag rc - flag, od - flag device id, rc - flag, od - flag write scratchpad read scratchpad copy scratchpad read memory pio access read pio access write pio access pulse reset act. latch write register 32 - byte scratchpad, flags 32 - byte scratchpad data memory, register page data memory, registers pio pins pio pins, activity latch pio pins, activity latch activity latch conditional search an d control registers 64 - bit device id number (network address) each ds28e04 - 100 has a un ique device id number that is 64 bits long , as shown in figure 3 . the first 8 bits are a 1 - wire family code. the next 8 bits are an external address byte, of which the lower 7 bits are connected to the address input pins a0 to a6. this allows the user to s et a portion of the device id number by connecting some of these pins to gnd (logic 0) or to v cc (logic 1) or leaving them open (logic 1). the next 4 0 bits are a lasered serial number. even if multiple ds28e04 - 100 are used in a 1 - wire network and all addre ss inputs are wired to the same state or left open (unconnected), the unique 40 - bit serialization field will prevent any address conflict, allowing to communicate with each device individually. the last 8 bits are a lasered crc (cyclic redundancy check) of the first 56 bits , assuming that the address input pins a0 to a6 are at logic 1. the 1 - wire crc is generated using a polynomial generator consisting of a shift register and xor gates as shown in figure 4. the polynomial is x 8 + x 5 + x 4 + 1. further inform ation on the device id crc is found in section crc generation near the end of this document. figure 3. 64 - bit device id number msb lsb 8 - bit crc code 40- bit lasered serial number 8 - bit external address input 8 - bit family code (1ch) 0 a 6 a 5 a 4 a 3 a 2 a 1 a 0 msb lsb msb lsb msb lsb msb lsb ds28e04 - 100: 4096- bit 1 - wire addressable eeprom with pio 7 of 37 figure 4. 1 - wire crc generator x 0 x 1 x 2 x 3 x 4 x 5 x 6 x 7 x 8 polynomial = x 8 + x 5 + x 4 + 1 1 st stage 2 nd stage 3 rd stage 4 th stage 6 th stage 5 th stage 7 th stage 8 th stage input data memory the ds28e04 - 100 eeprom array consists of 17 pages of 32 bytes each, starting at address 0000h and ending at address 021fh. all memory add resses in this range have unrestricted read access. the data memory consists of 16 pages of 32 bytes each. the register page consists of 32 bytes starting at address 0200h. it contains 16 page protection control bytes (one for each data memory page), the r egister page lock byte, the factory bytes, and the reserved bytes. the reserved bytes are for future use by the factory and should be not be used. they have no effect on device operation. the protection control registers, along with the register page loc k byte, determine whether write protection, eprom mode, or copy protection is enabled for each of the 16 data memory pages. a value of 55h sets write protection for the associated memory page. a value of aah sets eprom mode. a value of 55h or aah for the r egister page lock byte sets copy protection for all write - protected data memory pages, as well as the register page. eprom mode pages are not affected. the protection control registers and the register page lock byte write protect themselves if set to 55h or aah. any other setting leaves them open for unrestricted write access. in addition to the eeprom, the device has a 32 - byte volatile scratchpad. writes to the eeprom array are a two- step process. first, data is written to the scratchpad through the wri te scratchpad command, and then copied into the main array through the copy scratchpad command. the user can verify the data written to the scratchpad through the read scratchpad command prior to copying into the main array. if a memory location is write protected, data sent by the master to the associated address during a write scratchpad command is not loaded into the scratchpad. instead, it is replaced by the data in eeprom located at the target address. if a memory location is in eprom mode, the scrat chpad is loaded with the logical and of the data sent by the master and the data in eeprom at the target address. copy scratchpad commands to write - protected or eprom mode memory locations are allowed. this allows write - protected data in the device to be r efreshed, i.e., reprogrammed with the current data. if a memory location is copy protected, a copy scratchpad command to that location will be blocked, which is indicated by ffh success bytes. copy protection is used for a higher level of security, and sh ould only be used after all write - protected pages and their associated protection control bytes are set to their final values. copy protection as implemented with this device does not prevent copying data from one device to another; it only blocks the exec ution of the copy scratchpad command with a target address of a copy - protected memory page. ds28e04 - 100: 4096- bit 1 - wire addressable eeprom with pio 8 of 37 figure 5. memory map address locations 0000h to 021fh are nonvolatile. address locations 0220h to 0225 are volatile. address range type description protection c odes (notes) 0000h to 001fh r/(w) data memory page 0 (protection controlled by address 0200h) 0020h to 003fh r/(w) data memory page 1 (protection controlled by address 0201h) 0040h to 005fh r/(w) data memory page 2 (protection controlled by address 0202 h) 0060h to 007fh r/(w) data memory page 3 (protection controlled by address 0203h) 0080h to 009fh r/(w) data memory page 4 (protection controlled by address 0204h) 00a0h to 00bfh r/(w) data memory page 5 (protection controlled by address 0205h) 00c0h to 0dfh r/(w) data memory page 6 (protection controlled by address 0206h) 00e0h to 00ffh r/(w) data memory page 7 (protection controlled by address 0207h) 0100h to 011fh r/(w) data memory page 8 (protection controlled by address 0208h) 0120h to 013fh r/ (w) data memory page 9 (protection controlled by address 0209h) 0140h to 015fh r/(w) data memory page 10 (protection controlled by address 020ah) 0160h to 017fh r/(w) data memory page 11 (protection controlled by address 020bh) 0180h to 019fh r/(w) data memory page 12 (protection controlled by address 020ch) 01a0h to 01bfh r/(w) data memory page 13 (protection controlled by address 020dh) 01c0h to 01dfh r/(w) data memory page 14 (protection controlled by address 020eh) 01e0h to 01ffh r/(w) data memory page 15 (protection controlled by address 020fh) 0200h 1) to 020fh 1) r/(w) protection control pages 0 to 15 55h: write protected; aah: eprom mode. address 0200h is associated with memory page 0, address 0201h with page 1, etc. 0210h 1) r/(w) register page lock (see text) 0211h r factory byte (reads 55h or aah) 0212h to 021dh n/a reserved 021eh to 021fh r factory bytes (undefined value) 220h r pio logic state (the lower two bits are valid) 221h r pio output latch state (the lower two bits are valid) 222h r pio activity latch state (the lower two bits are valid) 223h r/w 2) conditional search pio selection mask 224h r/w 2) conditional search polarity selection 225h r/w 2) conditional search control and status register 1) once programmed to aah or 55h this address becomes read - only. all other codes can be stored but will neither write - protect the address nor activate any function. 2) limited write access through write register command ds28e04 - 100: 4096- bit 1 - wire addressable eeprom with pio 9 of 37 pio- related registers figure 6 shows the simplified logi c diagram of a pio channel. the registers related to the pio pins are located in the address range 0220h to 0225h. all these registers are volatile, i.e., they lose their state when the device is powered down. all pio - related registers can be read like any data memory. there are special commands to control the pios for input (read), output (write), pulse - generation, and to reset the activity latches. figure 6. pio simplified logic diagram pio out put latch pio acti vity latch edge detector port function control to activity latch state register to pio logic state register to pio output latch state reg. r q d d q q q "1" clr act latch p0, p1 data clock power on reset pio logic state register addr b7 b6 b5 b4 b3 b2 b1 b0 0220h 1 1 1 1 1 1 p1 p0 t he logic state of the pio pins can be obtained by reading this register using the read memory command. this register is read - only. each bit is associated with the pin of the respective pio channel . bits 2 to 7 h ave no function; they always read 1. the data in this register reflects the pio state at the last (most significant) bit of the byte that proceeds reading the first (least significant) bit of this register. see the pio access read command description for d etails. pio output latch state register addr b7 b6 b5 b4 b3 b2 b1 b0 0221h 1 1 1 1 1 1 pl1 pl0 the data in this register represents the latest data written to the pios through the pio access write command. this register is read using the read memory command. this register is not affected if the device re - initializes itself after an esd hit. this register is read - only. each bit is associated with the output latch of the respective pio channel . bits 2 to 7 have no function; they always read 1. the flip - flops of this register power up as specified by the state of the pol pin. if the chip has to power up with all pio channels off, the pol pin must be connected to a logic "1". ds28e04 - 100: 4096- bit 1 - wire addressable eeprom with pio 10 of 37 pio activity latch state register addr b7 b6 b5 b4 b3 b2 b1 b0 0222h 0 0 0 0 0 0 al1 al0 the data in this register represents the current state of the pio activity latches. this register is read using the read memory command. this register is read - only. each bit is associated with the activity latch of the respective pio channel . bits 2 to 7 have no function; they always read 0. a state transition on a pio pin, high ? low or low ? high, of a duration greater than t pw min causes the associated bit in the register to be set to a 1. this register is cleared to 00h by a power - on reset, or b y successful execution of the reset activity latches command. the next three registers control the device's participation a conditional search rom sequence. the interaction of the various signals that determine whether the device responds to a conditional search is illustrated in figure 7. there is a selection mask, sm, to select the participating pios, a polarity selection sp to specify for each channel whether the channel signal needs to be 1 or 0 to qualify, and a pls bit to select either the activity l atches or pio pins as inputs. the signals of all channels are fed into an and gate as well as an or gate. the ct bit finally selects the and ed or or ed result as the conditional search response signal csr. if ct is 0, the channel signal of at least one of the selected channels must match the corresponding polarity. if ct is 1, the channel signals of all selected channels must match the corresponding polarity. figure 7. conditional search l ogic al1 p1 pls sp0 sm0 ct sm1 sp1 al0 p0 csr channel 0 channel 1 porl conditional search channel se lection mask register addr b7 b6 b5 b4 b3 b2 b1 b0 0223h 0 0 0 0 0 0 sm1 sm0 the data in this register controls whether a pio channel qualifies for participation in the conditional search command. to include a pio channel , the bits in this register that correspond to those channels need to be set to 1. this register can only be written through the write register command. this register is read/write. each bit is associated with the respective pio channel as shown in figure 7 . bits 2 to 7 have no function; they always read 0 and cannot be changed to 1. this register is cleared to 00h by a power - on reset. ds28e04 - 100: 4096- bit 1 - wire addressable eeprom with pio 11 of 37 conditional search channel polarity selection register addr b7 b6 b5 b4 b3 b2 b1 b0 0224h 0 0 0 0 0 0 sp1 sp0 the data in this register specifies the p olarity of each selected pio channel for the device to respond to the conditional search command. this register can only be written through the write registers command. within a pio channel, the data source may be either the channel's input pin or the chan nel's activity latch, as specified by the pls bit in the control/status register at address 0225h. this register is read/write. each bit is associated with the respective pio channel as shown in figure 7 . bits 2 to 7 have no function; they always read 0 an d cannot be changed to 1. this register is cleared to 00h at power - up. control/status register addr b7 b6 b5 b4 b3 b2 b1 b0 0225h vccp pol 0 0 porl 0 ct pls the data in this register reports status information and further configures the device for co nditional search. this register can only be written through the write registers command. this register is read/write. the power - up state of the porl bit is "1". ct and pls power up as "0". the functional assignments of the individual bits are explained in the table below. bits 2, 4, and 5 have no function; they always read 0 and cannot be set to 1. control/status register details bit description bit(s) definition pls: pin or activity latch select b0 selects either the pio pins or the pio activity latches as input for the conditional search. 0: pin selected (default) 1: activity latch selected ct: conditional search logical term b1 specifies whether the data of two channels needs to be or ed or anded to meet the qualifying condition for the device to respond to a conditional search. if only a single channel is selected in the channel selection mask (0223h) this bit is a don't care. 0: bitwise or (default) 1: bitwise and porl: power - on reset latch b3 specifies whether the device has performed a pow er - on reset. this bit can only be cleared to 0 by writing to the control/status register. as long as this bit is 1 the device will always respond to a conditional search rom sequence. pol: pio default polarity (read - only) b6 reports the state of the pol pin. the state of the pol pin specifies whether the pio pins p0 and p1 power up high or low. the polarity of a pulse generated at a pio pin is the opposite of the pin's power - up state. 0: pio powers up 0 1: pio powers up 1 vccp: v cc power status (read - only) b7 for v cc - powered operation, the v cc pin needs to be connected to a voltage source equal to v pup . 0: v cc power not available 1: v cc - powered operation ds28e04 - 100: 4096- bit 1 - wire addressable eeprom with pio 12 of 37 address registers an d transfer status t he ds28e04 - 100 employs three address registers, called ta1, ta2, and e/s (figure 8 ). registers ta1 and ta2 must be loaded with the target address to which the data will be written or from which data is read . register e/s is a read - only transfer - status register, used to verify data integrity of write commands. the lower five bits of the e/s register indicate the ending offset within the 32 - byte scratchpad. bit 5 of the e/s register, called pf, is set if the number of data bits sent by the master is not an integer multiple of 8 or if the data in the scratchpad i s not valid due to a loss of power. a valid write to the scratchpad clears the pf bit. bit 6 has no function; it always reads 0. note that the lowest five bits of the target address also determine the address within the scratchpad, where intermediate stora ge of data will begin. this address is called byte offset. if the target address (ta1) for a write command is 03ch for example, then the scratchpad stores incoming data beginning at the byte offset 1ch and is full after only four bytes. the corresponding e nding offset in this example is 1fh. for maximum data bandwidth, the target address for writing should point to the beginning of a new page, i.e., the byte offset is 0. thus the full 32 - byte capacity of the scratchpad is available, resulting also in the en ding offset of 1fh. however, it is possible to write one or several contiguous bytes somewhere within a page. the ending offset together with the partial flag support the master checking the data integrity after a write command. the highest valued bit of t he e/s register, called aa is valid only if the pf flag reads 0. if pf is 0 and aa is 1, a copy has taken place. writing data to the scratchpad clears th e aa flag. figure 8. address registers bit # 7 6 5 4 3 2 1 0 target address (ta1) t7 t6 t5 t4 t3 t 2 t1 t0 target address (ta2) t15 t14 t13 t12 t11 t10 t9 t8 ending address with data status (e/s) (read only) aa 0 pf e4 e3 e2 e1 e0 writing with verific ation to write data to the ds28e04 - 100 eeprom sections, the scratchpad has to b e used as intermediate storage. first the master issues the write scratchpad command to specify the desired target address, followed by the data to be written to the scratchpad. under certain conditions (see write scratchpad command) the master will receiv e an inverted crc16 of the command, address (actual address sent), and data (as sent by the master) at the end of the write scratchpad command sequence. knowing this crc value, the master can compare it to the value it has calculated to decide whether the communication was successful and proceed to the copy scratchpad command. if the master could not receive the crc16, it should use the read scratchpad command to verify data integrity. as a preamble to the scratchpad data, the ds28e04 - 100 repeats the target address ta1 and ta2 and sends the contents of the e/s register. if the pf flag is set, data did not arrive correctly in the scratchpad or there was a loss of power since data was last written to the scratchpad. the master does not need to continue reading ; it can start a new trial to write data to the scratchpad. similarly, a set aa flag together with a cleared pf flag indicates that the device did not recognize the write command. if everything went correctly, both flags are cleared and the ending offset i ndicates the address of the last byte written to the scratchpad. now the master can continue reading and verifying every data byte. after the master has verified the data, it can send the copy scratchpad command. this command must be followed exactly by th e data of the three address registers, ta1, ta2, and e/s. the master should obtain the contents of these registers by reading the scratchpad. ds28e04 - 100: 4096- bit 1 - wire addressable eeprom with pio 13 of 37 memory/control funct ion commands the memory/control function flow chart (figure 9) describes the protocols neces sary to access the memory and the pio pins of the ds28e04 -100 . examples on how to use these functions are included at the end of this document. the communication between master and ds28e04 -100 takes place either at standard speed (default, od = 0) or at ov erdrive peed (od = 1). if not explicitly set into the overdrive mode, the ds28e04 -100 powers up in standard speed. write scratchpad com mand [0f h] the write scratchpad command applies to the data memory, and the writeable addresses in the register page. af ter issuing the write scratchpad command, the master must first provide the 2 - byte target address, followed by the data to be written to the scratchpad. the data is written to the scratchpad starting at the byte offset of t 4 :t0. the ending offset (e4:e0) i s the byte offset at which the master stops writing data. only full data bytes are accepted. if the last data byte is incomplete, its content will be ignored and the partial byte flag pf will be set. when executing the write scratchpad command, the crc ge nerator inside the ds28e04 -100 (figure 1 8 ) calculates a crc of the entire data stream, starting at the command code and ending at the last data byte as sent by the master. this crc is generated using the crc16 polynomial by first clearing the crc generator and then shifting in the command code (0fh) of the write scratchpad command, the target addresses (ta1 and ta2) as supplied by the master , and all the data bytes. the master may end the write scratchpad command at any time. however, if the end of the scra tchpad is reached (e 4 :e0 = 11 11 1b), the master can send 16 read- time slots and receive the crc generated by the ds28e04 -100. if a write scratchpad is attempted to a write - protected location, the scratchpad is loaded with the data already in memory, rathe r than the data transmitted. similarly, if the target address page is in eprom mode, the scratchpad is loaded with the bitwise logical and of the transmitted data and data already in memory. read scratchpad comm and [aa h] the read scratchpad command allows verification of the target address and the scratchpad data. after issuing the command code, the master begins reading. the first two bytes are the target address. the next byte is the ending offset/data status byte (e/s) followed by the scratchpad data, w hich may be different from what the master originally sent. this is of particular importance if the target address is within the register page or a page in either write - protected or eprom modes. see the write scratchpad description for details. the master shoul d read e4:e0 - t4:t0+1 bytes , after which it receives the inverted crc 16 , based on data as it was sent by the ds28e04 - 100 . if the master continues reading after the crc, all data will be logic 1s. copy scratchpad [55 h] the copy scratchpad command is u sed to copy data from the scratchpad to the data memory and the writable sections of the register page. after issuing the copy scratchpad command, the master must provide a 3 - byte authorization pattern, which should have been obtained by an immediately pre ceding read scratchpad command. this 3 - byte pattern must exactly match the data contained in the three address registers (ta1, ta2, e/s, in that order). if the pattern matches, the target address is valid, the pf flag is not set, and the target memory is n ot copy - protected, the aa (authorization accepted) flag is set and the copy begins. the data to be copied is determined by the three address registers. the scratchpad data from the beginning offset through the ending offset will be copied to memory, starti ng at the target address. anywhere from 1 to 32 bytes can be copied with this command. the devices internal data transfer takes 10ms maximum during which the voltage on the 1 - wire bus must not fall below 2.8v. after waiting 10ms, the master may issue read time slots to receive aah confirmation bytes until the master issues a reset pulse. if the pf flag is set or the target memory is copy - protected, the copy will not begin and the aa flag will not be set. ds28e04 - 100: 4096- bit 1 - wire addressable eeprom with pio 14 of 37 figure 9 - 1. memory/control function flow chart 0fh write scratch - pad ? bus master tx eeprom array target address ta1 (t7:t0), ta2 (t15:t8) y n to figure 9 2 nd part from figure 9 2 nd part bus master tx memory function command to rom functions flow chart (figure 14) from rom functions flow chart (figure 14) master tx reset ? master tx data byte to scratchpad offset n y ds28e04 sets scratchpad offset = (t4:t0 ), clears pf, aa scrpad. offset = 11111b? ds28e04 tx crc16 of command, address, dat a bytes as they were sent by the bus master ds28e04 increments scratchpad offset master tx reset ? y n bus master rx 1s n partial byte ? pf = 1 y n y applies only if the page is not write protected or in eprom mode. if write - protected, then the ds28e04 copies the data byte from the target address into the scratchpad. if in eprom mode, then the ds28e04 stores the bitwise logical and o f the transmitted byte and the data byte from the targeted address into the scratchpad. ds28e04 - 100: 4096- bit 1 - wire addressable eeprom with pio 15 of 37 figure 9 - 2. memory/control function flow chart (continued) aah read scratch- pad ? ds28e04 sets scratchpad offset = (t4:t0) bus master rx ta1 (t7:t0), ta2 (t15:t8) and e/s byte bus master rx data byte from scratchpad offset bus master rx crc16 of command, address, e/s byte, data bytes as sent by the ds28e04 y bus master rx 1s master tx reset ? y n master tx reset ? ds28e04 increments scratchpad offset scrpad . offset = e4 :e0 ? y y n n n from figure 9 1 st part to figure 9 1 st part to figure 9 3 rd part from figure 9 3 rd part see note in write scratchpad flow chart for additional details. ds28e04 - 100: 4096- bit 1 - wire addressable eeprom with pio 16 of 37 figure 9 - 3. memory/control function flow chart (continued) from figure 9 2 nd part to figure 9 2 nd part to figure 9 4 th part from figure 9 4 th part * 1 - wire idle high 10ms for power 55h copy scratch - pad ? bus master tx ta1 (t7:t0), ta2 (t15:t8) and e/s byte y n bus master rx 1s master tx reset ? y n y auth. code match ? n n copy - protected ? y ds28e04 copies scratch - pad data to address aa = 1 * ds28e04 tx 0 master tx reset ? master tx reset ? y n ds28e04 tx 1 n y applicable to all r/w memory locations. y t15:t0 < 0220h ? n pf = 0 ? y n ds28e04 - 100: 4096- bit 1 - wire addressable eeprom with pio 17 of 37 figure 9 - 4. memory/control function flow chart (continue d) ds28e04 - 100: 4096- bit 1 - wire addressable eeprom with pio 18 of 37 figure 9 - 5. memory/control function flow chart (continued) ds28e04 - 100: 4096- bit 1 - wire addressable eeprom with pio 19 of 37 figure 9 - 6. memory/control function flow chart (continued) ds28e04 - 100: 4096- bit 1 - wire addressable eeprom with pio 20 of 37 read memory [f0 h] the read memory command is the general function to read data from the ds28e04 - 100. after issuing the command, the master must provide a 2 - byte target address in the range of 0000h to 0225h. after these two bytes, the master reads data beginning from the target address and may continue until address 0225h. if the master continues reading, the result will be logic 1s. the device's internal ta1, ta2, e/s, and scratchpad contents are not affected by a read memory command. the hardware of the ds28e04 - 100 provides a means to accomplish error - free writing to the memory section. to safeguard reading data in the 1 - wire environment and to simultaneously speed up data transfers, it is recommended to packetize data into data packets the size of one memory page each. such a packet would typically st ore a 16 - bit crc with each page of data to insure rapid, error - free data transfers that eliminate having to read a page multiple times to determine if the received data is correct or not. (see application note 114 for the recommended file structure.) writ e register [cc h] the conditional search settings and the status/control register are volatile. they need to be loaded after every power - up cycle with the write register command. after issuing the command, the master sends the 2- byte target address, which s hould be a value between 0223h and 0225h. next the master sends the byte to be written to the addressed cell. if the address was valid, the byte is immediately written to its memory location. the master now can either end the com mand by issuing a 1 - wire r eset or send another byte for the next higher address. once memory address 0225h has been written, any subsequent data bytes will be ignored. the master has to send a 1 - wire reset to end the command. since the write register flow does not include any error - checking for the new register data, it is important to verify correct writing by reading the registers using the read memory command. pio access read [f5 h] in contrast to reading the pio logical state from address 0220h, this command reads the pio logic al status in an endless loop. after 32 bytes of pio pin status the ds28e04 - 100 inserts an inverted crc16 into the data stream, which allows the master to verify whether the data was received error - free. a pio access read can be terminated at any time with a 1- wire reset. the state of the pol pin does not affect this command. the status of both pio channels is sampled at the same time. the first sampling occurs during the last (most significant) bit of the command code f5h. the first (least significant) bit of the pio status byte is associated to p0, and the next bit to p1. the other 6 bits of a pio status byte do not have corresponding pio pins; they always read "1". while the master receives the last bit of the pio status byte, the next sampling occurs and so on until the master has received 32 pio samples. next the master receives the inverted crc16 of the command byte and 32 pio samples (first pass) or the crc of 32 pio samples (subsequent passes). while the last (most significant) bit of the crc is trans mitted, the next pio sampling takes place. the sampling occurs with a delay of t reh + x from the rising edge of the ms bit of the previous byte, as shown in figure 10. the value of "x" is approximately 0.2s. figure 10. pio access read timing diagram io example - sampled state = feh ms 2 bits of previous byte ls 2 bits of data byte ( feh) v th sampling point t reh +x notes: 1 the "previous byte" could be the command code, the data byte resulting from the previous pio sample, or the ms byte of a crc16. 2 the sample point timing also applies to the pio access write and pulse command, with the "prev ious byte" being the write confirmation byte (aah). ds28e04 - 100: 4096- bit 1 - wire addressable eeprom with pio 21 of 37 pio access write [5a h] the pio access write command is the only way to write to the pio output - latch state register (address 0221h), which controls the open - drain output transistors of the pio channels. in an endless loop, this command first writes new data to the pio and then reads back the pio status. the implicit read - after - write can be used by the master for status verification. a pio access write can be terminated at any time with a 1 - wire reset. the state of the pol pin does not affect this command. after the command code, the master transmits a byte that determines the new state of the pio output transistors. the first (least significant) bit is associated to p0; the next bit affects p1. the other 6 bits of the new state byte do not have corresponding pio pins. these bits should always be transmitted as "1"s. to switch the output transistor off (nonconducting) the corresponding bit value is 1. to switch the transistor on, that bit needs to be 0. thi s way the data byte transmitted as the new pio output state arrives in its true form at the pio pins. to protect the transmission against data errors, the master must repeat the new pio byte in its inverted form. only if the transmission was error - free doe s the pio status change. the actual pio transition to the new state occurs with a delay of t reh + x from the rising edge of the ms bit of the inverted pio byte, as shown in figure 11. the value of "x" is approximately 0.2s. to inform the master about the successful change of the pio status, the ds28e04 - 100 transmits a confirmation byte with the data pattern aah. after the ms bit of the confirmation byte is transmitted, the ds28e04 - 100 samples the status of the pio pins, as shown in figure 10, and sends it to the master. depending on the data the master can either continue writing more data to the pio or issue a 1 - wire reset to end the command. figure 11. pio access write timing diagram io pio example - old state = feh, new state = fdh ms 2 bits of inverted new-state byte ls 2 bits of confir- mation byte (aah) feh fdh v th t reh +x pio access pulse [a5h] as a convenient alternative to using pio access write, the pio access pulse command generates a self - timed pulse on the selected pio outputs. the polarity of the pulse is determined by the state of the pol pin. if pol = 1, the pulse is negative (active low) and vice versa . the pio access pulse command is accepted only if the device is v cc powered. after the command code the master transmits a selection mask that specifies the pio at which the pulse is to be generated. a pio is selected if the corresponding bit in the sel ection mask is a "1". the first (least significant) bit is associated to p0; the next bit affects p1. the other 6 bits of the selection mask do not have corresponding pio pins. these bits should always be transmitted as "1"s. to protect the transmission ag ainst data errors, the master must repeat the selection mask in its inverted form. only if the transmission was error - free does the pulse occur. the pulse begins with a delay of t reh + x from the rising edge of the ms bit of the inverted selection mask, as shown in figure 12. the value of "x" is approximately 0.2s. to inform the master about the successful pulse generation, the ds28e04 - 100 transmits a confirmation byte with the data pattern aah. while the last bit of the confirmation byte is transmitted, t he ds28e04 - 100 samples the status of the pio pins, as shown in figure 10, and sends it to the master. now the master can issue a 1 - wire reset to exit the command flow. this does not terminate the pulse on a pio pin. ds28e04 - 100: 4096- bit 1 - wire addressable eeprom with pio 22 of 37 figure 12. pio access pulse timing dia gram t pulse io pio ms 2 bits of inverted selection mask ls 2 bits of confir- mation byte (aah) v th t reh +x pol=1 pol=0 reset activity latch es [c3 h] each pio channel includes an activity latch that is set whenever there is a state transition at a pio pin of duration greater than t pwmin . this change can be caused by an external event/signal or by writing to the pio or by generating a pulse. depending on the application there may be a need to reset the activity latch after having captured and serviced an external event. since there is only read access to the pio activity latch state register, the ds28e04 - 100 supports a special command to reset these latches. after having received the command code, the device resets all activity latches simultaneously. there are two ways for the master to verify the execution of the reset activity latches comma nd. one way is to start reading from the 1 - wire line right after the command code is transmitted. in this case, the master reads aah bytes until it sends a 1 - wire reset. the other way is reading register address 0222h. 1- wire bus system the 1 - wire bus i s a system that has a single bus master and one or more slaves. in all instances the ds28e04 - 100 is a slave device. the bus master is typically a microcontroller. the discussion of this bus system is broken down into three topics: hardware configuration, t ransaction sequence, and 1 - wire signaling (signal types and timing). the 1 - wire protocol defines bus transactions in terms of the bus state during specific time slots, which are initiated on the falling edge of sync pulses from the bus master. hardware configuration the 1 - wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. to facilitate this, each device attached to the 1 - wire bus must have open - drain or tri - state outputs . the 1 - wire port of the ds28e04 -100 is open drain with an internal circuit equivalent to that shown in figure 13. a multidrop bus consists of a 1 - wire bus with multiple slaves attached. the ds28e04 -100 supports both a standard and overdrive communicatio n speed of 15.4kbps (max) and 111kbps (max), respectively. note that legacy 1 - wire products support a standard communication speed of 16.3kbps and overdrive of 142kbps. the slightly reduced rates for the ds28e04 -100 are a result of additional recovery time s, which in turn were driven by a 1 - wire physical interface enhancement to improve noise immunity. the value of the pullup resistor primarily depends on the network size and load conditions. the ds28e04 -100 requires a pullup resistor of 2.2k ? (max) at any speed. the idle state for the 1 - wire bus is high. if, for any reason, a transaction needs to be suspended, the bus must be left in the idle state if the transaction is to resume. if this does not occur and the bus is left low for more than 16s (overdriv e speed) or more than 120s (standard speed), one or more devices on the bus can be reset. ds28e04 - 100: 4096- bit 1 - wire addressable eeprom with pio 23 of 37 figure 13. hardware configuration open - drain port pin rx = receive tx = transmit 100 ? mosfet v pup rx tx tx rx data r pup 11a max. bus master ds28e04 1 - wire port transaction sequence the protocol for accessing the ds28e04 -100 through the 1 - wire port is as f ollows: ? initialization ? rom function command ? memory/control function command ? transaction/data initialization all transactions on the 1 - wire bus begin with an initialization sequence. the initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). the presence pulse lets the bus master know that the ds28e04 -100 is on the bus and is ready to operate. for more details, see the 1 - wire signaling section. 1- wire rom function commands once the bus master has detected a presence, it can issue one of the eight rom function commands that the ds28e04 -100 supports. all rom function commands are 8 bits long. a list of these commands follows (refer to the flow chart in figure 14). read rom [ 33 h] this command allows the bus master to read the ds28e04 -100 s 8 - bit family code, unique 40- bit serial number, 8- bit address byte, and 8 - bit crc. the lower order 7 bits of the address byte read back the state of the address pins a6 to a0. see also figur e 3. this command can only be used if there is a single slave on the bus. if more than one slave is present on the bus, a data collision occurs when all slaves try to transmit at the same time (open drain produces a wired - and result). the resultant family code and 48 - bit serial number result in a mismatch of the crc. note that there will also be a crc mismatch if one or more of the external address inputs are connected to gnd. the rom crc is hardcoded with a6 to a0 set to 1s. the master should comprehend th is and calculate the rom crc similarly. match rom [55 h] the match rom command, followed by a 64 - bit rom sequence, allows the bus master to address a specific ds28e04 -100 on a multidrop bus. only the ds28e04 -100 that exactly matches the 64 - bit rom sequence, including the external address, responds to the following memory/control function command. all other slaves wait for a reset pulse. this command can be used with a single or multiple devices on the bus. ds28e04 - 100: 4096- bit 1 - wire addressable eeprom with pio 24 of 37 search rom [f0 h] when a system is initially brough t up, the bus master might not know the number of devices on the 1 - wire bus or their device id numbers. by taking advantage of the wired - and property of the bus, the master can use a process of elimination to identify the device id numbers of all slave dev ices. for each bit of the device id number, starting with the least significant bit, the bus master issues a triplet of time slots. on the first slot, each slave device participating in the search outputs the true value of its device id number bit. on the second slot, each slave device participating in the search outputs the complemented value of its device id number bit. on the third slot, the master writes the true value of the bit to be selected. all slave devices that do not match the bit written by the master stop participating in the search. if both of the read bits are zero, the master knows that slave devices exist with both states of the bit. by choosing which state to write, the bus master branches in the romcode tree. after one complete pass, the bus master knows the device id number of a single device. additional passes identify the device id numbers of the remaining devices. refer to application note 187: 1 - wire search algorithm for a detailed discussion, including an example. note: since the d s28e04 - 100 lasered rom crc is calculated assuming the address inputs are all logic 1, then any address inputs that are connected to gnd are not validated. it is recommended to do a double search when building a list of devices on the 1 - wire line. conditi onal search [ec h] the conditional search rom command operates similarly to the search rom command except that only those devices, which fulfill certain conditions (csr = 1), will participate in the search. this function provides an efficient means for the bus master to identify devices on a multidrop system that have to signal an important event. after each pass of the conditional search that successfully determined the 64 - bit rom code for a specific device on the multidrop bus, that particular device can b e individually accessed as if a match rom had been issued, since all other devices will have dropped out of the search process and will be waiting for a reset pulse. the ds28e04 - 100 responds to the conditional search if the csr signal is active. see the de scription of the registers at addresses 0223h to 0225h and figure 7 for more details. skip rom [cch] this command can save time in a single - drop bus system by allowing the bus master to access the memory functions without providing the 64 - bit rom code. i f more than one slave is present on the bus and, for example, a read command is issued following the skip rom command, data collision occurs on the bus as multiple slaves transmit simultaneously (open - drain pulldowns produce a wired- and result). resume [a 5h] to maximize the data throughput in a multidrop environment, the resume function is available. this function checks the status of the rc bit and, if it is set, directly transfers control to the memory functions, similar to a skip rom command. the only w ay to set the rc bit is through successfully executing the match rom, search rom, or overdrive match rom command. once the rc bit is set, the device can repeatedly be accessed through the resume command function. accessing another device on the bus clears the rc bit, preventing two or more devices from simultaneously responding to the resume command function. overdrive skip rom [ 3c h] on a single - drop bus this command can save time by allowing the bus master to access the memory functions without providing the 64 - bit rom code. unlike the normal skip rom command, the overdrive skip rom sets the ds28e04 -100 in the overdrive mode (od = 1). all communication following this command has to occur at overdrive speed until a reset pulse of minimum 480s duration res ets all devices on the bus to standard speed (od = 0). when issued on a multidrop bus, this command sets all overdrive - supporting devices into overdrive mode. to subsequently address a specific overdrive - supporting device, a reset pulse at overdrive speed has to be issued followed by a match rom or search rom command sequence. this speeds up the time for the search process. if more than one slave supporting overdrive is present on the bus and the overdrive skip rom command is followed by a read command, da ta collision occurs on the bus as multiple slaves transmit simultaneously (open - drain pulldowns produce a wired - and result). ds28e04 - 100: 4096- bit 1 - wire addressable eeprom with pio 25 of 37 figure 14 - 1. rom functions flow chart from figure 14 2 nd part to memory functions flow chart (figure 9) master tx bit 0 master tx bit 63 master tx bit 1 rc = 1 ds28e04 tx family code (1 byte) bit 0 match? y n bit 1 match? y n bit 63 match? y n ds28e04 tx bit 0 ds28e0 4 tx bit 0 master tx bit 0 ds28e04 tx bit 1 ds28e04 tx bit 1 master tx bit 1 ds28e04 tx bit 63 ds28e04 tx bit 63 master tx bit 63 rc = 1 bit 0 match? y n bit 1 match? y n bit 63 match? y n to figure 14 2 nd part rc = 0 rc = 0 rc = 0 rc = 0 y y y y n f0h search rom command? n 55h match rom command? n ech cond. search command? n 33h read rom command? to figure 14 2 nd part from memory functions flow chart (figure 9) bus master tx rom function command ds28e04 tx presence pulse od reset pulse? n y od = 0 bus master tx reset pulse from figure 14, 2 nd part csr = 1? y n ds28e04 tx bit 0 ds28e04 tx bit 0 master tx bit 0 ds28e04 tx bit 1 ds28e04 tx bit 1 master tx bit 1 ds28e04 tx bit 63 ds28e04 tx bit 63 master tx bit 63 rc = 1 bit 0 match? y n bit 1 match? y n bit 63 match? y n ds28e04 tx crc byte ds28e04 tx ext. address (7 bits) ds28e04 tx serial number (40 bits) ds28e04 tx "0" (1 bit) the crc is hard - coded assuming all external address bits ar e 1's. ds28e04 - 100: 4096- bit 1 - wire addressable eeprom with pio 26 of 37 figure 14 - 2. rom functions flow chart (continued) from figure 14 1 st part from figure 14 1 st part to figure 14, 1 st part rc = 1 ? n y rc = 0 ; od = 1 master tx bit 0 master tx bit 63 master tx bit 1 rc = 1 bit 0 match? y n bit 1 match? y n bit 63 match? y n y n 69h overdrive match rom? rc = 0 ; od = 1 master tx reset ? y n master tx reset ? n y y n 3ch overdrive skip rom? y n a5h re sume command? rc = 0 y n cch skip rom command? to figure 14 1 st part ds28e04 - 100: 4096- bit 1 - wire addressable eeprom with pio 27 of 37 overdrive match rom [69 h] the overdrive match rom command followed by a 64 - bit rom sequence transmitted at overdrive speed allows the bus master to address a specific ds28e04 -100 on a multidrop bus and to simultaneously set it in overdrive mo de. only the ds28e04 -100 that exactly matches the 64 - bit rom sequence responds to the subsequent memory/control function command. slaves already in overdrive mode from a previous overdrive skip or successful overdrive match command remain in overdrive mode . all overdrive - capable slaves return to standard speed at the next reset pulse of minimum 480s duration. the overdrive match rom command can be used with a single or multiple devices on the bus. 1-wire signaling the ds28e04 - 100 requires strict protocols to ensure data integrity. the protocol consists of four types of signaling on one line: reset sequence with reset pulse and presence pulse, write - zero, write - one, and read- data. except for the presence pulse, the bus master initiates all falling edges. th e ds28e04 - 100 can communicate at two different speeds, standard speed, and overdrive speed. if not explicitly set into the overdrive mode, the ds28e04 - 100 communicates at standard speed. while in overdrive mode, the fast timing applies to all waveforms. to get from idle to active, the voltage on the 1 - wire line needs to fall from v pup below the threshold v tl . to get from active to idle, the voltage needs to rise from v ilmax past the threshold v th . the time it takes for the voltage to make this rise is see n in figure 15 as ' ' and its duration depends on the pullup resistor (r pup ) used and the capacitance of the 1 - wire network attached. the voltage v ilmax is relevant for the ds28e04 - 100 when determining a logical level, not triggering any events. figure 1 5 shows the initialization sequence required to begin any communication with the ds28e04 - 100. a reset pulse followed by a presence pulse indicates the ds28e04 - 100 is ready to receive data, given the correct rom and memory/control function command. if the bus master uses slew - rate control on the falling edge, it must pull down the line for t rstl + t f to compensate for the edge. a t rstl duration of 480s or longer exits the overdrive mode, returning the device to standard speed. if the ds28e04 - 100 is in over drive mode and t rstl is no longer than 80s, the device remains in overdrive mode. if the device is in overdrive mode and t rstl is between 80s and 480s, the device will reset, but the communication speed is undetermined. figure 15. initialization proc edure: reset and presence pulse after the bus master has released the line, it goes into receive mode. now the 1 - wire bus is pulled to v pup through the pullup resistor, or in case of a ds2482 - x00 or ds2480b driver, by active ci rcuitry. when the threshold v th is crossed, the ds28e04 - 100 waits for t pdh and then transmits a presence pulse by pulling the line low for t pdl . to detect a presence pulse, the master must test the logical state of the 1 - wire line at t msp . the t rsth wind ow must be at least the sum of t pdhmax , t pdlmax , and t recmin . immediately after t rsth is expired, the ds28e04 - 100 is ready for data communication. in a mixed population network, t rsth should be extended to minimum 480s at standard speed and 48s at overdr ive speed to accommodate other 1 - wire devices. ds28e04 - 100: 4096- bit 1 - wire addressable eeprom with pio 28 of 37 read/write time slots data communication with the ds28e04 - 100 takes place in time slots, which carry a single bit each. write time slots transport data from bus master to slave. read time slots transfer data from slave to master. figure 16 illustrates the definitions of the write and read time slots. all communication begins with the master pulling the data line low. as the voltage on the 1 - wire line falls below the threshold v tl , the ds28e04 - 100 starts its internal timing generator that determines when the data line is sampled during a write time slot and how long data is valid during a read time slot. figure 16. read/write timing diagram write - one time slot resistor master v pup v ihmaster v th v tl v ilmax 0v t f t slot t w1l write - zero time slot resistor master t rec v pup v ihmaster v th v tl v ilmax 0v t f t slot t w0l read - data time slot ds28e04 - 100: 4096- bit 1 - wire addressable eeprom with pio 29 of 37 master -to- slave for a write - one time slot, the voltage on the data line must have crossed the v th threshold before the write - one low time t w 1lmax is expired. for a write -ze ro time slot, the voltage on the data line must stay below the v th threshold until the write - zero low time t w0lmin is expired. for the most reliable communication, the voltage on the data line should not exceed v ilmax during the entire t w0l or t w1l window. after the v th threshold has been crossed, the ds28e04 - 100 needs a recovery time t rec before it is ready for the next time slot. slave -to- master a read - data time slot begins like a write - one time slot. the voltage on the data line must remain below v tl un til the read low time t rl is expired. during the t rl window, when responding with a 0, the ds28e04 - 100 starts pulling the data line low; its internal timing generator determines when this pulldown ends and the voltage starts rising again. when responding w ith a 1, the ds28e04 - 100 does not hold the data line low at all, and the voltage starts rising as soon as t rl is over. the sum of t rl + (rise time) on one side and the internal timing generator of the ds28e04 - 100 on the other side define the master sam pling window (t msrmin to t msrmax ) in which the master must perform a read from the data line. for the most reliable communication, t rl should be as short as permissible, and the master should read close to but no later than t msrmax . after reading from the data line, the master must wait until t slot is expired. this guarantees sufficient recovery time t rec for the ds28e04 - 100 to get ready for the next time slot. note that t rec specified herein applies only to a single ds28e04 - 100 attached to a 1- wire line. f or multidevice configurations, t rec needs to be extended to accommodate the additional 1 - wire device input capacitance. alternatively, an interface that performs active pullup during the 1 - wire recovery time such as the ds2482 - x00 or ds2480b 1- wire line dr ivers can be used. improved network beh avior (switchpoint h ysteresis) in a 1 - wire environment, line termination is possible only during transients controlled by the bus master (1 - wire driver). 1 - wire networks, therefore, are susceptible to noise of vario us origins. depending on the physical size and topology of the network, reflections from end points and branch points can add up, or cancel each other to some extent. such reflections are visible as glitches or ringing on the 1 - wire communication line. noi se coupled onto the 1 - wire line from external sources can also result in signal glitching. a glitch during the rising edge of a time slot can cause a slave device to lose synchronization with the master and, consequently, result in a search rom command com ing to a dead end or cause a device - specific function command to abort. for better performance in network applications, the ds28e04 - 100 uses a new 1- wire front end, which makes it less sensitive to noise and also reduces the magnitude of noise injected by the slave device itself. the 1 - wire front end of the ds28e04 - 100 differs from traditional slave devices in four characteristics. 1) the falling edge of the presence pulse has a controlled slew rate. this provides a better match to the line impedance than a digitally switched transistor, converting the high - frequency ringing known from traditional devices into a smoother low - bandwidth transition. the slew - rate control is specified by the parameter t fpd , which has different values for standard and overdrive s peed. 2) there is additional lowpass filtering in the circuit that detects the falling edge at the beginning of a time slot. this reduces the sensitivity to high - frequency noise. this additional filtering does not apply at overdrive speed. 3) there is a hyster esis at the low -to - high switching threshold v th . if a negative glitch crosses v th but does not go below v th - v hy , it will not be recognized (figure 17, case a). the hysteresis is effective at any 1 - wire speed. 4) there is a time window specified by the risi ng edge hold - off time t reh during which glitches are ignored, even if they extend below v th - v hy threshold (figure 17, case b, t gl < t reh ). deep voltage droops or glitches that appear late after crossing the v th threshold and extend beyond the t reh window cannot be filtered out and are taken as the beginning of a new time slot (figure 17, case c, t gl t reh ). only devices that have the parameters t fpd , v hy , and t reh specified in their electrical characteristics use the improved 1 - wire front end. ds28e04 - 100: 4096- bit 1 - wire addressable eeprom with pio 30 of 37 figure 1 7. noise suppression scheme v pup v th v hy 0v t reh t gl t reh t gl case a case c case b crc generation with the ds28e04 -100 there are two different types of crcs. one crc is an 8 - bit type and is stored in the most significant byte of the 64 - bit rom. the bus master can compute a crc value from the first 56 bits of the rom and, if none of the address inputs is connected to gnd, compare it to the value stored within the ds28e04 -100 to determine whether the rom data has been received error - free. if any of the address pins are connected t o gnd, the bus master can calculate the crc based on an all 1s external address field to determine whether the non - external address rom data has been received error - free. the equivalent polynomial function of this crc is x 8 + x 5 + x 4 + 1. this 8 - bit crc is received in the true (noninverted) form. it is computed at the factory and hardcoded into the rom. the other crc is a 16 - bit type, generated according to the standardized crc16- polynomial function x 16 + x 15 + x 2 + 1. this crc is used for fast verificatio n of a data transfer when writing to or reading from the scratchpad or when reading from the pios. in contrast to the 8 - bit crc, the 16- bit crc is always communicated in the inverted form. a crc generator inside the ds28e04 -100 chip (figure 18) calculates a new 16 - bit crc, as shown in the command flow chart (figure 9). the bus master compares the crc value read from the device to the one it calculates from the data, and decides whether to continue with an operation or to reread the portion of the data with the crc error . with the write scratchpad command, the crc is generated by first clearing the crc generator and then shifting in the command code, the target addresses ta1 and ta2, and all the data bytes as they were sent by the bus master. the ds28e04 -100 transmits this crc only if e4:e0 = 11111b, i.e., the end of the scratchpad is hit. with the read scratchpad command, the crc is generated by first clearing the crc generator and then shifting in the command code, the target addresses ta1 and ta2, the e/ s byte, and the scratchpad data as they were sent by the ds28e04 -100 . the ds28e04 -100 transmits this crc only if the reading continues through the end of the data written in the previous write scratchpad sequence. example: if one writes a single byte to th e scratchpad and then reads the scratchpad, one will receive a crc of the command, ta1, ta2, and the data byte. with the initial pass through the pio access read command flow, the crc is generated by first clearing the crc generator and then shifting in the command code followed by 32 bytes of pio pin data. subsequent passes through the command flow generate a 16 - bit crc that is the result of clearing the crc generator and then shifting in 32 bytes read from the pio pins. for more information on generatin g crc values, refer to application note 27 . ds28e04 - 100: 4096- bit 1 - wire addressable eeprom with pio 31 of 37 figure 18. crc - 16 hardware description and polynomial polynomial = x 16 + x 15 + x 2 + 1 x 0 x 1 x 2 x 3 x 4 x 5 x 6 x 7 x 8 x 9 x 10 x 11 x 12 x 13 x 14 x 15 x 16 1 st stage 2 nd stage 3 rd stage 4 th stage 6 th stage 5 th stage 7 th stage 8 th stage 9 th stage 10 th stage 11 th stage 12 th stage 13 th stage 14 th stage 15 th stage 16 th stage input data crc output command - specific 1 -wire communication protoc ol legend symbol description rst 1 - wire reset pulse generated by master. pd 1 - wire presence pulse generated by slave. select command and data to satisfy the rom function protocol. ws command "write scratchpad". rs command "read scratchpad". cps command "copy scratchpad". rm command "read memory". wreg command "write register". pior command "pio access read". piow command "pio access write". piop command "pio access pulse". ral command "reset activity latches". ta target address ta1, ta2. ta - e/s target address ta1, ta2 with e/s byte. <32 C t4:t0 bytes> transfer of as many bytes as needed to reach the end of the scratchpad for a given target address. transfer of as many data bytes as are needed to reach the end of the memory. ds28e04 - 100: 4096- bit 1 - wire addressable eeprom with pio 32 of 37 command - specific 1 -wire communication protoc ol color codes master to slave slave to master programming write scratchpad (ca nnot fail) rst pd select ws ta <32 C t4:t0 bytes> crc16\ ff loop read scratchpad (can not fail) rst pd sel ect rs ta - e/s ds28e04 - 100: 4096- bit 1 - wire addressable eeprom with pio 33 of 37 pio access read (can not fail) rst pd select pior <32 bytes pio data> crc16\ pio access write (su ccess) rst pd select piow ds28e04 - 100: 4096- bit 1 - wire addressable eeprom with pio 34 of 37 memory function exam ple write 5 bytes to memory page 1, starting at address 0021h. read the entire memory and the pio - related registers. with only a single ds28e04 -100 conne cted to the bus master, the communication looks like this: master mode data (lsb first) comments tx (reset) reset pulse rx (presence) presence pulse tx cch issue skip rom command tx 0fh issue write scratchpad command tx 21h ta1, beginning offset = 21h tx 00h ta2, address = 00 21h tx <5 data bytes> write 5 bytes of data to scratchpad tx (reset) reset pulse rx (presence) presence pulse tx cch issue skip rom command tx aah issue read scratchpad command rx 21h read ta1, beginning offset = 21 h rx 00h read ta2, address = 00 21h rx 05h read e/s, ending offset = 00101b, aa, pf = 0 rx <5 data bytes> read scratchpad data and verify rx <2 bytes crc16 \ > read crc to check for data integrity tx (reset) reset pulse rx (presence) presence pulse tx cch issue skip rom command tx 55h issue copy scratchpad command tx 21h ta1 tx 00h ta2 (authorization code) tx 05h e/s ---- <1 - wire idle high> wait 10ms for the copy function to complete rx aah read copy status, aah = success tx (reset) reset pu lse rx (presence) presence pulse tx cch issue skip rom command tx f0h issue read memory command tx 00h ta1, beginning offset = 00h tx 00h ta2, address = 00 00h rx <550 data bytes> read the entire memory tx (reset) reset pulse rx (presence) prese nce pulse ds28e04 - 100: 4096- bit 1 - wire addressable eeprom with pio 35 of 37 pio access read exam ple read the state of the pios 32 times. with only a single ds28e04 -100 connected to the bus master, the communication looks like this: master mode data (lsb first) comments tx (reset) reset pulse rx (presence) presence pulse tx cch issue skip rom command tx f5h issue pio access read command rx <32 data bytes> read 32 pio samples rx <2 bytes crc16 \ > read crc to check for data integrity tx (reset) reset pulse rx (presence) presence pulse the inverted crc16 is t ransmitted after 32 bytes of pio data. pio access write exa mple set both pios to 0 and then to 1. both pios are pulled high to v cc or v pup by a resistor. with only a single ds28e04 -100 connected to the bus master, the communication looks like this: m aster mode data (lsb first) comments tx (reset) reset pulse rx (presence) presence pulse tx cch issue skip rom command tx 5ah issue pio access write command tx fch write new pio output state tx 03h write inverted new pio output state rx aah read confirmation byte rx fch read new pio pin status tx ffh write new pio output state tx 00h write inverted new pio output state rx aah read confirmation byte rx ffh read new pio pin status tx (reset) reset pulse rx (presence) presence pulse ds28e04 - 100: 4096- bit 1 - wire addressable eeprom with pio 36 of 37 pio acc ess pulse example generate a pulse on pio1. both pios are pulled high to v cc by a resistor. pol = 1. v cc power is present. with only a single ds28e04 -100 connected to the bus master, the communication looks like this: master mode data (lsb first) comment s tx (reset) reset pulse rx (presence) presence pulse tx cch issue skip rom command tx a5h issue pio access pulse command tx feh write pio selection mask tx 01h write inverted pio selection mask rx aah read confirmation byte rx 1111110xb read p io pin status 1) tx (reset) reset pulse rx (presence) presence pulse 1) the "x" indicates the state of pio0, which is not defined in this example. package information for the latest package outline information and land patterns (footprints), go to www.maxim - ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 16 so s16+1 21-0041 90-0097 ds28e04 - 100: 4096- bit 1 - wire addressable eeprom with pio 37 of 37 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no cir cuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408 - 737 - 7600 ? 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision date description pages changed 102704 initial release 12/11 changed the ordering information for lead(pb) - free product ; updated the lead temperature and soldering temperature ; e xtende d the s torage temperature range . 1, 2 in the electrical characteristi cs table a pplied note 19 to the t w0l specification , d eleted from the t w1l specification , increased the data retention time, a dded more details to notes 10, 19 and 20 , and added notes 23, 24. 3, 4 added package information section and revision history . 36, 37 |
Price & Availability of DS28E04-100
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |